1. Field of Invention
The present invention relates to an interleaving and de-interleaving circuit. More particularly, the present invention relates to a convolutional interleaving and de-interleaving circuit and method applicable for the Digital Video Broadcast (DVB) system.
2. Description of Related Art
The technology of convolutional interleaving circuit and convolutional de-interleaving circuit is widely used in the fields of telecommunication, as Global System for Mobile communication (GSM), Synchronous Digital Hierarchy (SDH), Digital Video Broadcast-Terrestrial (DVB-T). Such technology is used mainly to prevent the data transmission channel from the interference of noise.
During data transmission, noise or some unsatisfactory effects of the channels often causes data errors. Previously, the method of Error Correcting Code (ECC), such as Hamming Code, was used to correct errors. However, the ECC has a limitation for the number of error bits. When unsatisfactory effects of the channels cause too many errors or continuous error bits, the ECC can not correct the errors. To avoid continuous error bits and too many errors within the same data, it is necessary to use the technology of convolutional interleaving circuit and convolutional de-interleaving circuit.
FIG. 1 is a schematic block diagram of a conventional convolutional interleaving circuit and convolutional de-interleaving circuit. Referring to FIG. 1, the block 101 is the convolutional interleaving circuit and the convolutional de-interleaving circuit is block 102. The convolutional interleaving circuit 101 includes a serial to parallel converting device 111, a plurality of shift registers 121 and a parallel to serial converting device 131. The convolutional de-interleaving circuit 102 includes a serial to parallel converting device 112, a plurality of shift registers 122 and a parallel to serial converting device 132.
When a serial input data D_IN inputs to the convolutional interleaving circuit 101, the serial input data D_IN will go through the serial to parallel converting device 111 first to be converted into parallel data, which are the outputs 0˜31 of the serial to parallel converting device 111, respectively. Wherein, the data “0” is outputted to the parallel to serial converting device 131 directly, the data “1” is outputted to the shift register 121; after delaying for a preset time, the data “1” is outputted to the parallel to serial converting device 131. The data “2” is outputted to the shift register 121, after delaying for one preset time, the data “2” is outputted to the next shift register 121; and after delaying for another preset time, the data “2” is outputted to the parallel to serial converting device 131. Similarly, the data “31” is outputted to the parallel to serial converting device 131 after delaying for 31 times of the preset time. The parallel to serial converting device 131 receives the data 0˜31, converts the data 0˜31 to the serial output data D_OUT and outputs it.
Similarly, the convolutional de-interleaving circuit 102 works under the same principle. The serial input data D_IN will go through the serial to parallel converting device 112 first to be converted into parallel data 0˜31. The difference is that the data “0” is delayed for 31 times of the preset time, and the data “30” is delayed for one preset time while the data “31” is not delayed. However, a great number of the shift registers in the integrated circuit will result in a waste of the area.
U.S. Pat. No. 5,537,420 proposed a convolutional interleaving and convolutional de-interleaving circuit as shown in FIG. 2. The circuit includes N address accumulators 200, an address selector 202, a memory 204 and a controller 206. These address accumulators 200 provide address pointers to the address selector 202. The address selector 202 selects an address pointer from one of the address accumulators 200 as the memory address. The memory 204 writes the data into the memory or reads the data from the memory according to the reading/writing commands of the controller 206 and the memory address from the address selector 202. Basically, the above described patent utilizes a random access memory to implement convolutional interleaving and convolutional de-interleaving circuit.
Compared to the conventional architecture shown in FIG. 1, the architecture saves a lot of gate counts. Take the Digital Video Broadcast-Terrestrial (DVB-T) system as an example, there are about 60K transistor used as shown in FIG. 1. In the U.S. Pat. No. 5,537,420, only 2K transistors are used. However, the U.S. Pat. No. 5,537,420 still has to use a lot of adders and high bit registers that unavoidably increases a lot of unnecessary gate counts and limits the chip layout.